SISO

Serial-in / Serial-out shift register

Serial-in/ serial-out shift registers delay data by one clock time for each stage. They will store a bit of data for each register. A serial-in/ serial-out shift register may be one to 64 bits in length, longer if registers or packages are cascaded.

Figure 1 shows a single stage shift register receiving data which is not synchronized to the register clock. The “data in” at the D pin of the type D FF (Flip-Flop) does not change levels when the clock changes for low to high. We may want to synchronize the data to a system wide clock in a circuit board to improve the reliability of a digital logic circuit.

Figure 1: Serial-in/Serial-out Shift operation using D-Flip-flop

Figure 2: Timing diagram of Serial data in and Serial Out operation

In Figure 2 it is illustrated that whatever “data in” is present at the D pin of a type D FF is transferred from D to output Q at clock time. Since our example shift register uses positive edge sensitive storage elements, the output Q follows the D input when the clock transitions from low to high as shown by the up arrows on the diagram above. There is no doubt what logic level is present at clock time because the data is stable well before and after the clock edge. This is seldom the case in multi-stage shift registers. But, this was an easy example to start with. We are only concerned with the positive, low to high, clock edge. The falling edge can be ignored. It is very easy to see Q follow D at clock time above. Compare this to the diagram below where the “data in” appears to change with the positive clock edge.

Self Assessment Questions

1. Which of the output is correct QC or QW ?

Solution:

Since “data in” appears to changes at clock time t1 above, what does the type D FF see at clock time? The short over simplified answer is that it sees the data that was present at D prior to the clock. That is what is transferred to Q at clock time t1. The correct waveform is QC. At t1 Q goes to a zero if it is not already zero. The D register does not see a one until time t2, at which time Q goes high.

Timings in Serial Shift operation

Figure 3: Timing illustration of Serial data in and Serial Out operation

Since data, above, present at D is clocked to Q at clock time, and Q cannot change until the next clock time, the D FF delays data by one clock period, provided that the data is already synchronized to the clock. The QA waveform is the same as “data in” with a one clock period delay.

A more detailed look at what the input of the type D Flip-Flop sees at clock time follows. Since “data in” appears to changes at clock time, we need further information to determine what the D FF sees. To summarize, output Q follows input D at nearly clock time if Flip-Flops are cascaded into a multi-stage shift register.

Serial In, Serial out Shift operation – 3 register combination

Figure 4: Three register operation of Serial data in and Serial Out using D Flip-flops

Three type D Flip-Flops are cascaded Q to D and the clocks paralleled to form a three stage shift register above.

Figure 5: Three register operation of Serial data in and Serial Out using J-K Flip-flops

Type JK FFs cascaded Q to J, Q’ to K with clocks in parallel to yield an alternate form of the shift register above.

A serial-in/serial-out shift register has a clock input, a data input, and a data output from the last stage. In general, the other stage outputs are not available Otherwise it would be a serial-in, parallel-out shift register.

The waveforms below in figure 6 are applicable to either one of the preceding two versions of the serial-in, serial-out shift register. The three pairs of arrows show that a three stage shift register temporarily stores 3-bits of data and delays it by three clock periods from input to output.

Figure 6:Timing diagrams of 3-shift register Serial data in, Serial data out operation

At clock time t1 a “data in” of 0 is clocked from D to Q of all three stages. In particular, D of stage A sees a logic 0, which is clocked to QA where it remains until time t2.

At clock time t2 a “data in” of 1 is clocked from D to QA. At stages B and C, a 0, fed from preceding stages is clocked to QB and QC.

At clock time t3 a “data in” of 0 is clocked from D to QA. QA goes low and stays low for the remaining clocks due to “data in” being 0. QB goes high at t3 due to a 1 from the previous stage. QC is still low after t3 due to a low from the previous stage.

QC finally goes high at clock t4 due to the high fed to D from the previous stage QB. All earlier stages have 0s shifted into them. And, after the next clock pulse at t5, all logic 1s will have been shifted out, replaced by 0s

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