Ring counters If
the output of a shift register is fed back to the input, a ring counter
results. The data pattern contained within the shift register will
recirculate as long as clock pulses are applied. For example, the data
pattern will repeat every four clock pulses in the figure below.
However, we must load a data pattern. All 0’s or all 1’s doesn’t count.  Figure 1: Ring Counter We
make provisions for loading data into the parallel-in/ serial-out shift
register configured as a ring counter below. Any random pattern may be
loaded. The most generally useful pattern is a single 1.  Figure 2: Parallel–in/serial–out shift register configured as Ring Counter Loading
binary 1000 into the ring counter, above, prior to shifting yields a
viewable pattern. The data pattern for a single stage repeats every
four clock pulses in our 4-stage example. The waveforms for all four
stages look the same, except for the one clock time delay from one
stage to the next. See figure 3.  Figure 3: Timing diagram of Ring counter with 1000 loaded |