Unit 4 CPU and Register Organization
Structure:
4.1 Introduction
Objectives
4.2 Registers
User-Visible Registers
Control and Status Registers
Program Status Word (PSW)
4.3 CPU Organization
Fundamental Computer Architecture
CPU organization in 8085 microprocessor
4.4 Register Organization of different machine
The Zilog Z8000 machine
Intel 8086 machine
Motorola 68000 machine
4.5 Instruction cycles
Basic instruction cycle
Basic instruction Cycle state diagram
4.6 Summary
4.7 Terminal Questions
4.8 Answers
4.1 Introduction
As discussed in the previous unit a CPU consists of a set of
registers that function as a level of memory above Main memory and Cache
memory. The registers in the CPU are of two types:
· User-visible Registers: These enable the machine or assembly
language programmer to minimize main memory references by use of
registers.
· Control and Status Registers: These are used by the control
unit to control the operation of the CPU and by privileged operating
system programs to control the execution of programs.
Note: Sometimes there is no clear separation of registers into
these categories. For example, on some of the machines the register
called Program Counter (PC) is user visible, that is, user can see the
contents of PC, but on some machines it is invisible to the user.
Objectives:
By the end of Unit 4, the learners should be able to:
1. Explain the register organization of any basic computer.
2. Explain status word, program counter registers.
3. Discuss the register organization of Intel 8085 microprocessor and
compare with other machines.
4. Explain the different phases of basic instruction cycle.
4.2 Registers
User-Visible Registers
User visible registers are those registers that are used by the user
in the machine language and can be executed by the CPU. All CPU designs
provide a number of user visible registers. These registers can be
categorized into following different types:
· General Purpose Registers: They can be assigned a variety of
functions by the programmer. The general purpose registers can be
considered for orthogonal usage and non-orthogonal usage.
-If any general purpose register can contain the operand for any
opcode then we refer the use of general purpose as orthogonal usage.
-Sometimes the use of general purpose register is restricted. For
example, there may be dedicated registers that are used for floating
point operations. Then we refer to the use of general purpose as non
orthogonal usage.
· Data registers: They can only be used to hold data, and
cannot be employed in the calculation of an operand address.
· Address registers: They may be used either in general
purpose addressing modes, or may be devoted to a particular addressing
mode.
-Segment Pointers: In a machine CPU with segmented addressing,
a register holds the address of the base of a segment. There may be
multiple segment registers. For example, one for the operating system,
one for the current process.
For example, Intel 8086 family has different segments and they are
referred to as
1) code segment: where the code is written
2) data segment: where the data is placed
3) stack segment: acts like a stack
4) extra segment
Thus there may be many registers one for operating system and one for
the current process.
-Index Registers: These are used for indexed addressing, and
may be auto indexed.
-Stack Pointer: If there is a user-visible stack addressing,
then typically the stack is in memory and there is a dedicated register
that points to the top of the stack. This allows implicit addressing,
that is push, pop and other stack instructions need not contain an
explicit stack operand.
· Condition codes: These are least partially visible register
types. They are also referred to as flags. The bits of Flag register are
set according to the result of an operation. There can be Zero flag,
Carry flag, etc., that indicate whether the result is zero or the result
produced an overflow, respectively.
Example: Consider the length of all registers to be two bits long.
The result of adding two binary numbers 10 and 11 will be 101. That is
1) The result will be stored in a destination register which will be
01.
2) And the carry is set as there is overflow after execution.
Control and Status Registers
These registers are employed to control the operation of the CPU.
Four registers are essential to instruction execution:
· Program Counter (PC): It contains the address of an
instruction to be fetched.
· Instruction Register (IR): It contains the instruction most
recently fetched.
· Memory Address Register (MAR): It contains the address of a
location in memory.
· Memory Buffer Register (MBR): It contains a word of data to
be written to memory or the word most recently read.
These four registers are used for the movement of data between the
CPU and memory.
Within the CPU, data must be presented to the ALU for processing. The
ALU may have direct access to the MBR and user-visible registers.
Alternatively, there may be additional buffering registers at the
boundary to the ALU; and these registers serve as input and output
registers for the ALU and exchange data with MBR and user-visible
registers. This depends on the design of the CPU and ALU.
Program Status Word (PSW):
It contains status information. PSW typically contains condition
codes plus other status information. Some of these may be user visible.
Common flags include:
· Sign: contains the sign bit of the result of the last
arithmetic operation.
· Zero: set when the result is 0.
· Carry: set if an operation resulted in a carry (addition)
into or borrow (subtraction) out of the high-order bit.
· Equal: set if logical compare result is equality.
· Overflow: used to indicate arithmetic overflow.
· Interrupt enable/disable: used to enable or disable
interrupts.
· Supervisor: Indicates whether the CPU is executing in
supervisor mode or user mode. Certain privilege instructions can be
executed only in supervisor mode (e.g. halt instruction), and certain
areas of memory can be accessed only in supervisor mode.
4.3 CPU organization
Figure 4.1: CPU with System Bus
As discussed earlier CPU which is the heart of a computer consists of
Registers, Control Unit and Arithmetic Logic Unit. The interconnection
of these units is achieved through the system bus as shown in figure
4.1.
The following tasks are to be performed by the CPU:
1. Fetch instructions: The CPU must read instructions from the
memory.
2. Interpret instructions: The instructions must be decoded to
determine what action is required.
3. Fetch data: The execution of an instruction may require
reading data from memory or an I/O module.
4. Process data: The execution of an instruction may require
performing some arithmetic or logical operations on data.
5. Write data: The results of an execution may require writing
data to the memory or an I/O module.
Fundamental Computer Architectures
Here we describe the most common Computer Architectures, all of which
use stored program control concept.
The three most popular computer architectures are:
1) The Stack Machine
2) The Accumulator Machine
3) The Load / Store Machine
The Stack Machine
A stack machine implements a stack with registers. The operands of
the ALU are always the top two registers of the stack and the result
from the ALU is stored in the top register of the stack. Examples of the
stack machine include Hewlett-Packard RPN calculators and the Java
Virtual Machine (JVM).
Figure 4.2: The Stack Machine Architecture
The advantage of a stack machine is that it can shorten the length of
instructions since operands are implicit. This was important when
memory was expensive (20–30 years ago). Now, in Java, it is important
since we want to ship executables (class files) over the network.
The Accumulator Machine
An accumulator machine has a special register, called an accumulator,
whose contents are combined with another operand as input to the ALU,
with the result of the operation replacing the contents of the
accumulator.
accumulator = accumulator [op] operand;
Figure 4.3: The Accumulator Machine Architecture
In fact, many machines have more than one accumulator
Pentium: 1, 2, 4 or 6 (depending on how you count)
MC68000: 16
In order to add two numbers in memory,
1) Place one of the numbers into the accumulator (load operand)
2) Execute the add instruction
3) Store the contents of the accumulator back into memory (store
operand)
The Load/Store Machine
Registers: Provide faster access but are expensive.
Memory: Provides slower access but is less expensive.
A small amount of high speed memory (expensive), called a register
file, is provided for frequently accessed variables and a much
larger but slower memory (less expensive) is provided for the rest of
the program and data. (SPARC: 32 register at any one time)
This is based on the principle of “locality" – at a given time, a
program typically accesses a small number of variables much more
frequently than others.
Figure 4.4: The Load / Store Machine Architecture
The machine loads and stores the registers from memory. The
arithmetic and logic instructions operate with registers, not main
memory, for the location of operands.
Since the machine addresses only a small number of registers, the
instruction field to refer to a register (operand) is short; therefore,
these machines frequently have instructions with three operands:
ADD src1, src2, dest
EXAMPLE MACHINE INSTRUCTIONS
y = y+10
y¢ º &y
[y¢] º *&y¢ = *& y = y
Stack Machine Accumulator Machine Load / Store Machine
Push [y¢] Load
[y¢] Load
r0, [y¢]
Push 10 Add 10
Load r1, 10
Add Store
y’ Add r0, r1, r2
Pop y’
Store r2, y’
CPU organization of 8085 microprocessor
In the following sections we will take a look at the CPU organization
in Intel 8085. We will study the register organization and their
relationship with other components in a relatively simple Intel 8085.The
Intel 8085 CPU organization is as shown in figure 4.5.
The CPU of 8085 is organized around a single 8-bit internal bus.
Connected to the Bus are the following components.
1. Accumulator: Used as a temporary buffer to
store input to the ALU. It is also user visible and is addressed in some
instructions.
2. Temporary register: Used as input for ALU
this is other than Accumulator.
3. Flags: These are nothing but condition codes.
The result of ALU operations are related back in the register as flags.
Figure 4.5: Intel 8085 CPU organization
The different flag bits supported by the 8085 CPU are:
1. Z: It stands for Zero Flag. This bit is set when the result
of ALU operation is zero. That is result = zero implies Z=1 and result =
non zero implies Z=0.
2. S: It stands for Sign Flag. This bit is set when the result
of ALU operation is negative
That is result = negative implies S=1 and result = non negative
implies
S=0
3. P: It stands for Parity Flag. This bit is set when the
result of ALU operation results in even parity. That is the result when
expressed in binary has even number of ones in it.
That is result contains even number of ones implies even parity P=1
and result contains odd number of ones implies odd parity P=0
4. CY: It stands for Carry Flag. This bit is set when the
result of ALU operation results in overflow.
That is result contains overflow implies carry flag (CY) =1 and
result does not contain overflow implies CY=0
5. AC: It stands for Auxiliary Carry Flag. This bit is set
when the result of
ALU operation results in carry between fourth and fifth bit.
That is result contains carry from fourth to fifth bit implies AC = 1
and result contains carry from fourth to fifth bit implies AC =0
4. ALU output: The result of an operation is
placed on the bus.
5. Instruction register: It is loaded from the
memory buffer register (MBR) through the Bus. The instruction is brought
into CPU through the address/data buffer and internal CPU bus to the
instruction register. Then it is decoded here and executed by the
control unit.
6. Register Array: It is a collection of
registers that are user visible and help to store the operands or result
of the operation.
The register array contains five 16-bit registers. The B – C, D – E, H
– L register, Stack pointer and program register.
1. The first three types of registers can be treated as a single 16
bit register each or two 8-bit registers each. That is B, C, D, E, H, L
are six registers which are 8-bit long.
2. Stack pointer is a 16-bit that points to the location of stack
memory. This is used for stack oriented machines.
3. Program counter is 16 bit that points to the current location of
the memory where the instructions are to be written. It is moved to the
MAR (address plus address/data buffers) to begin the fetching of the
next instruction.
Any of these registers may be loaded, 8-bits at a time, from the
internal bus or transferred to the address buffer or address/data
buffer. Also any of the 16-bit registers can be transferred to the MAR
that connects to the external address bus.
7. Address/data Buffer: This buffer connects to
multiplexed bus lines. Some of the time, this buffer acts as a memory
buffer register (MBR) to exchange data with the system bus. At other
times it acts as the low order 8-bits of a memory address register
(MAR). This multiplexing allows additional pins that are available for
control signals to the system bus.
8. Address buffer: Used as a high order 8 bits
of the MAR.
Let us consider an instruction ADD B as an example to study the
sequence of actions that takes place.
· This instruction causes the contents of register B to be added to
the contents of the accumulator.
· To execute this instruction, the control unit moves the contents of
register B to the temporary register.
· The ALU performs the add operation on its inputs.
· The result is placed on the internal CPU bus and copied into the
accumulator.
· The ALU also updates the flags to reflect the results of add.
4.4 Register Organization of different machines
It is very much instructive to examine and compare the register
organization of comparable systems. In this section we will discuss the
register organization of 16-bit microprocessors that were developed more
or less at the same time.
The Zilog Z8000
Figure 4.6 depicts the register organization of Z8000 machine. Here
only purely internal registers structure is given and memory address
registers are not shown.
Figure 4.6: Zilog Z8000 register organization
Z8000 consists of sixteen 16-bit general purpose registers, which can
be used for data, address and indexing. The designers of this machines
felt that it was useful to provide a regularized, general set of
registers than to save instruction bits by using special purpose
registers. Further the way the functions are assigned to these registers
is the responsibility of the programmer. There might be different
functional breakdown for different applications.
A segmented address space uses 7-bit segment number and a 16-bit
offset. It uses two registers to hold a single address. There are two
other registers called stack pointers that are necessary for stack
module. One register used for system mode and one for normal mode.
Z8000 consists of five other registers that are related to program
status. Two registers hold the program counter and two registers hold
the address of a program status area in the memory. A 16-bit flag
register called Flag control word holds various flags status and
control bits.
Intel 8086
The approach taken by Intel for register organization is different
than Z8000 machine and is as shown in Figure 4.7.
Figure 4.7: Intel 8086 register organization
In this machine every register is a special purpose register. There
are some registers that also serve as general purpose registers. The
8086 machine contains four 16-bit data registers that are accessible on a
byte or 16-bit basis. It also has four 16-bit pointers and index
registers. The data registers can be used as general purpose registers
in some instructions. In others registers are used implicitly.
Example: A multiply instruction always uses accumulator. The four
pointer registers each with segment offset are also used in a number of
operations implicitly. There are also four segment registers. Three of
these segment registers are used in a dedicated, implicit way to point
to the segment of the current instruction, a segment containing data and
a segment containing a stack. This type of structure is useful in
branch operations. The dedicated and implicit uses provide for compact
encoding at the cost of reduced flexibility. The 8086 also includes an
instruction pointer and a set of 1 bit status and control flags.
The Motorola MC68000
Figure 4.8: MC68000 register organization
This machine uses a structure that falls between the Zilog Z8000 and
Intel 8086. The register organization of MC68000 is as shown in figure
4.8
The MC6800 machine partitions the 32-bit registers into eight data
registers and nine address registers. The data registers are used in
data manipulations and are also used in addressing only as index
registers. The width of data register allows 8-bit, 16-bit and 32-bit
data operations depending upon the opcode.
The address registers contain a 32-bit address. It does not support
segmentation. Two of the address registers are used as stack pointers:
One for the users and one for the operating system, depending upon the
current execution mode. Both the stack pointers are numbered as seven
i.e., A7 as only one can be used at a time. The MC68000 also has program
counter and status register as in the other two machines. The program
counter is 32-bit register and status register is 16-bit. Like Zilog the
Motorola team also supports a regular instruction set with no special
purpose registers. For the purpose of code efficiency they divided the
registers into functional components, saving one bit at each registers.
4.5 Instruction Cycles
The basic function performed by a computer is program execution. The
program to be executed consists of a set of instructions stored in
memory. The CPU does the actual work by executing the instructions
written in the program.
Basic Instruction cycle
To understand the ways the major components of a computer or rather
CPU interact to execute a program, consider the flow chart as shown in
figure 4.9.
Figure 4.9: Basic instruction cycle
The processing required for a single instruction is called an instruction
cycle. Referring to the above figure 4.9, the basic instruction
cycle can be assumed to consist of two steps:
1. The CPU reads or fetches instructions from memory one at a time.
2. Then this single instruction is executed.
The program execution consists of repeating these two steps of
instruction fetch and instruction execution until the end of the
program.
Thus the instruction cycles consists of fetch cycle and execute
cycle.
The execution of program itself may involve a number of steps. The
instruction fetch is a common operation for every instruction, and
consists of reading an instruction from a location in memory. The
instruction may involve several operations depending upon the nature of
the instructions. In any CPU we have seen that there is a register
called program counter that keeps track of the instructions to be
fetched next from the memory. CPU always increments the PC after each
instruction fetch so that it will fetch the next instructions in
sequence.
The fetched instruction is stored in a register in the CPU known as
instruction register. The instruction is in the form of binary code that
specifies what action has to be taken by the CPU. The CPU interprets
the instruction and performs the required action.
Example: If PC = [300] that is PC is set to 300 location of memory.
If there are three instructions in a program and next subsequent
instructions are placed say 303, 304 and end or Halt at 306. Then
discuss the steps involved in execution of this program.
Solution:
1. First of all the instruction that is present at location 300 in
memory is loaded into IR .At the same time PC is incremented by 3 as the
next instruction is at 303.
2. Depending on the instruction that is decoded, it finds that
operands are to be read from memory (as the next instruction is at 303
implies that the operands of first instruction may be placed at 301 and
302)
3. Then the instruction is executed.
4. Then again reads the instruction from 303 into IR and update
PC=304.
5. Decodes the instruction and Executes. (Now operands are definitely
not specified in memory as the next instruction is at 304.)
6. The third instruction is read into IR from location 304 as PC=304
and now PC updates with 306.
7. Decodes the instruction and may find operand in memory location
hence gets operands from memory at 305.
8. and then executes the instruction
9. Finally now the next instruction is at 306 so it is read in IR and
PC=307
10. Decodes this instruction which is halt
11. Executes it which terminates the execution of the program.
The following is one view of the instruction cycles:
· Fetch the instruction:
=>Place it in a holding area called IR.
=>Update the program counter (PC).
· Execute the instruction:
=>Decode the instruction:
-Perform address translation.
-Fetch operands from memory.
=>Perform the required calculation.
=>Store results in registers or memory.
=>Set status flags attached to the CPU.
The required action performed by the CPU falls into four categories.
1. CPU-Memory: Data may be transferred from the CPU to memory
or from memory to CPU
2. CPU-I/O: Data may be transferred to/from the outside world
by transferring between CPU and I/O module.
3. Data processing: The CPU may perform some arithmetic or
logic operations on data.
4. Control: An instruction may specify the sequence of
execution be altered. For example, jump instruction.
Consider for example that the program is written from location 300 to
320 in the memory. Now if the instruction present at say 305 is
something like jump to 310. When the program is executed the instruction
located at 300 to 305 are executed in sequence one at a time. Then
after the execution of instruction jump to 310, the CPU has updated the
PC=310. Hence the next instruction that is fetched will be from 310 and
so on.
Basic Instruction Cycle State
diagram
These are the detailed states occurring during the fetch and
execution cycles are as shown in figure 4.10. A few of them occur only
once and a few occur multiple times.
Figure 4.10: Instruction Cycle State Diagram
The different possible states occurring in Instruction cycle are:
· Instruction Address Calculation (IAC): Determine the address
of the next instruction to be executed. Usually, this involves adding a
fixed number to the address of the previous instruction. For example,
if each instruction is 16 bits long and memory is organized into 16-bits
words, then add 1 to the previous address. If, instead memory is
organized as individually addressable 8-bit bytes, then add 2 to the
previous address.
· Instruction Fetch (IF): Read instruction from its memory
location into the processor.
· Instruction Operation Decoding (IOD): Analyze instruction to
determine type of operation to be performed and operand(s) to be used.
· Operand Address Calculation (OAC): If the operation involves
reference to an operand in memory or available via I/O, then determine
the address of the operand.
· Operand Fetch (OF): Fetch the operand from memory or read it
in, from I/O.
· Data Operation (DO): Perform the operation indicated in the
instruction.
· Operand Store (OS): Write the result into memory or out to
I/O.
During the instruction cycles, Instruction address calculation,
Instruction fetch and Instruction operation decoding are performed only
once, but operand address calculation and operand fetch may happen
multiple times. Data operation is performed once, and Operand store with
the combination of Operand address calculation may be
performed zero or more times depending on the instruction.
4.6 Summary
We know that CPU consists of a set of registers that function as a
level of memory. Here we have discussed the different types of registers
like user visible registers, control registers or flag registers and so
on. We have also introduced the basic instruction cycle so as to get a
feel of how exactly these registers are used in the execution of the
instruction. As a case study we have seen the detail register
organization of few machines like Zilog Z8000, Intel 8086 and Motorola
68000 microprocessors.
Self Assessment Questions
1. CPU consists of a set of registers that function as a level of
memory above ______________.
2. ______________ enable the machine or assembly language programmer
to minimize main memory references by use of registers.
3. Flags of 8085 are nothing but ______________.
4. ______________ number of flag bits is defined in 8085.
5. The processing required for a single instruction is called an
______________ .
4.7 Terminal Questions
1. List and explain the various condition flags of the Intel 8085
microprocessor.
2. Explain the register organization of 8086.
3. Compare the register organization of 8085, Z8000 and MC68000.
4.8 Answers
Self Assessment Questions:
1. main memory and cache memory
2. user visible registers
3. conditional codes
4. five
5. instruction cycle
Terminal Questions:
1. Refer Section 4.3
2. Refer Section 4.4
3. Refer Section 4.4
